Time constant and variable-delay circuits have many applications, one of the most important being adjustment of the phase of a clock signal used in a complex synchronous system. This phase adjustment is intended to compensate for differences in synchronization that can be caused by electrical connections and especially by manufacturing differences. It is desirable for these parasitic delays, usually called "skew", to be corrected. Known delay circuits often use a dynamic phase lock loop, making them dependent on the clock frequency and ruling out their use for step-by-step operation. It is therefore appropriate to seek a solution among static operating circuits. They can be made from an RC type circuit where the resistance R ca be modified by control signals as a function of an adjusting value.
In addition, in the case of an embodiment in an integrated circuit, it is preferable for the adjusting value to be defined digitally to avoid problems related to technological variations. For this purpose, the circuit advantageously can consist of an RC circuit whose resistance R is composed of a plurality of elementary resistances selectively connected in parallel as a function of a digital control command.
On the other hand, the circuit is preferably designed to allow its easy integration into an integrated circuit employing MOS or CMOS technology or, more generally, one based on isolated-gate field effect transistors (IGFETs). In this context, the easiest way to obtain controlled resistance is to employ the drain-source lead of an MOS transistor, whose size governs the value of the resistance. The resistance can be included in the circuit in simple fashion by applying a control signal of the appropriate polarity to the transistor gate. Thus each MOS transistor fulfills the dual function of a switch and a resistor. Of course, a functionally equivalent embodiment could consist of replacing this transistor by a plurality of transistors of the same and/or complementary type, provided that in the latter case control signals of the correct polarity are applied to their gates. For example, a circuit called a "transfer gate" can be used, which consists of an NMOS transistor in parallel with a PMOS transistor, with their gates receiving control signals of opposite polarities.
Moreover, isolated gate transistors in the conducting state exhibit high capacitance between their gates and each of their other electrodes. Of course, an MOS transistor wired as a switch or a CMOS transfer gate constitutes an RC circuit. It is therefore a good idea to take advantage of this property by devising a time constant circuit composed primarily of MOS switches or CMOS transfer gates, with the capacitance C of the RC circuit then being the structural capacitance of the unit.
To adjust the time constant accurately, it must be possible to insert a high-value resistor selectively in parallel. In practice, the resistance of the drain-source lead of an MOS transistor is adjusted by varying the "width"of the transistor. Thus, in order to increase the resistance of the transistor, its width must be reduced. Since its length is essentially fixed for a given technology, the gate-drain or gate-source capacitances of the transistor will be reduced. On the other hand, the capacitive effect of the transistor is practically nonexistent except when it is conducting. It follows from the above that increasing the resistance of a transistor reduces the total capacitance of the circuit; this is the opposite of the desired effect, which is to increase the time constant. Consequently, in order to have a strong time constant, the resistance of the transistor must be increased to a much greater degree but its width must be reduced, rapidly leading to the lower limit imposed by the technology.
In addition, the maximum time constant is obtained when the transistor with the highest resistance is the only one that conducts. Because the other transistors are blocked, their contribution to the resultant capacitance of the circuit is practically zero.